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Astera LabsLaunch

Astera Labs unveils next-gen CXL controllers to accelerate agentic AI workloads

What happened

Astera Labs has launched the next generation of its Leo Compute Express Link (CXL) smart memory controllers, including the high-end X-Series, and the second generation of its E-series and P-series controllers.

Source

Article excerpt

Highlighted: the sentence this signal was extracted from

X-Series to aid offloading KV cache for AI inference Astera Labs unveiled the next generation of its Leo Compute Express Link (CXL) smart memory controllers. The vendor added a trio of devices, with the high-end X-Series touted for offloading key-value (KV) cache for high-intensity AI workloads. Paired with Astera's Scorpio network switch silicon, it's designed to provide larger cache capacity with low-latency access for agentic AI inference applications. Astera also unveiled the second generation of its E-and P-series controllers to boost both central processing units (CPUs) and rack-scale memory. The E-series provides direct CPU-attached memory expansion, adding extra capacity while reducing the need for an additional socket. The second-generation P-series pools memory across rack-scale platforms, reducing server over-provisioning to maximize available capacity. Smart memory controllers are essentially infrastructure add-ons, providing CPUs and graphics processing units (GPUs) with the means to connect to additional memory capacity for an extra oomph. They keep accelerators from idling by increasing the memory bandwidth available to processing cores. "Agentic AI is where the economics of AI infrastructure are being decided and those economics depend on putting every usable gigabyte of memory to work," Thad Omura, SVP of Astera's compute connectivity group, noted. "The...

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Event
Launch

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The full record

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Details

Product
Leo Compute Express Link (CXL) smart memory controllers
Release type
Generation

Topics and mentions

Product tags

  • general technology
  • data

Extraction

Confidence
90%
Detected
Sep 15, 2026
signal_type
news
signal_subtype
launches

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This page shows a preview. The full news record in the Signal API and MCP can also have these 8 fields. Some fields are empty for some signals.

Company

  • linkedin_urlValue in the API
  • industriesValue in the API
  • employee_count_lowValue in the API
  • employee_count_highValue in the API
  • revenueValue in the API
  • descriptionValue in the API

Signal

  • signal_nameValue in the API
  • associationValue in the API
Show the full JSONThe record on this page and the API request

GET /v1/signals/c76401de-08ce-8b0e-a59c-4a130a4a234d returns this record as JSON. POST /v1/companies/enrich returns every signal for asteralabs.com.

{
  "signal_id": "c76401de-08ce-8b0e-a59c-4a130a4a234d",
  "signal_type": "news",
  "signal_subtype": "launches",
  "detected_at": "2026-09-15T13:07:39+00:00",
  "company": {
    "name": "Astera Labs",
    "domain": "asteralabs.com"
  },
  "data": {
    "url": "https://www.sdxcentral.com/news/600-am-pt/",
    "title": "Astera Labs unveils next-gen CXL controllers to accelerate agentic AI workloads - SDxCentral",
    "excerpt": "X-Series to aid offloading KV cache for AI inference Astera Labs unveiled the next generation of its Leo Compute Express Link (CXL) smart memory controllers. The vendor added a trio of devices, with the high-end X-Series touted for offloading key-value (KV) cache for high-intensity AI workloads. Paired with Astera’s Scorpio network switch silicon, it’s designed to provide larger cache capacity with low-latency access for agentic AI inference applications. Astera also unveiled the second generation of its E-and P-series controllers to boost both central processing units (CPUs) and rack-scale memory. The E-series provides direct CPU-attached memory expansion, adding extra capacity while reducing the need for an additional socket. The second-generation P-series pools memory across rack-scale platforms, reducing server over-provisioning to maximize available capacity. Smart memory controllers are essentially infrastructure add-ons, providing CPUs and graphics processing units (GPUs) with the means to connect to additional memory capacity for an extra oomph. They keep accelerators from idling by increasing the memory bandwidth available to processing cores. “Agentic AI is where the economics of AI infrastructure are being decided and those economics depend on putting every usable gigabyte of memory to work,” Thad Omura, SVP of Astera’s compute connectivity group, noted. “The...",
    "product": "Leo Compute Express Link (CXL) smart memory controllers",
    "summary": "Astera Labs has launched the next generation of its Leo Compute Express Link (CXL) smart memory controllers, including the high-end X-Series, and the second generation of its E-series and P-series controllers.",
    "planning": false,
    "image_url": "https://media.datacenterdynamics.com/media/images/Leo-E-X-P.2e16d0ba.fill-1200x630.jpg",
    "confidence": 0.9,
    "product_data": {
      "name": "Leo Compute Express Link (CXL) smart memory controllers",
      "full_text": "Leo Compute Express Link (CXL) smart memory controllers",
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    "product_tags": [
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    "published_at": "2026-09-15T13:07:39Z",
    "article_sentence": "Astera Labs unveiled the next generation of its Leo Compute Express Link (CXL) smart memory controllers."
  }
}

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