Cadence PCIe 6.0 subsystem achieves first-pass compliance certification

{
  "signal_id": "000c530e-6328-5ae9-9c5f-340dcd55e238",
  "signal_type": "news",
  "signal_subtype": "achieves_certification",
  "detected_at": "2026-09-22T12:56:38+00:00",
  "company": {
    "name": "Cadence",
    "domain": "cadence.com"
  },
  "data": {
    "url": "https://www.myeverydaytech.com/cadence-pcie-6-0-first-pass-compliance/",
    "title": "Cadence PCIe 6.0 subsystem achieves first-pass compliance certification - myeverydaytech.com",
    "excerpt": "Cadence has announced that its PHY and controller IP for the PCIe 6.0 specification, built on TSMC’s N3 process, achieved first-pass success at the recent PCI-SIG compliance workshop held in late July, the industry’s first official event for testing PCIe 6.0 compliance. Specifically, the firm’s x8 subsystem solution was tested at the full PCIe 6.0 specification speed of 64 GT/s, with the complete subsystem, covering both PHY and controller, passing all official compliance tests and landing on PCI-SIG’s Integrators List. Thanks to the extensive groundwork done ahead of the formal workshop as well as collaboration between PCI-SIG, test equipment providers, and industry partners, they are able to run interoperability testing to catch and resolve potential issues before the official evaluation. PCIe 6.0 is designed to meet growing demand for high-bandwidth connectivity in AI and HPC systems, where it’s used across accelerator cards, network interfaces, and storage devices, with adoption expected to concentrate first in data centers and AI infrastructure before extending into automotive and enterprise systems as the ecosystem matures. As a matter of fact, Positron AI has licensed Cadence’s SerDes IP for PCIe 6.0 for its AI inference accelerator chip, adding that Cadence’s silicon-proven subsystem and robust interoperability testing give the company confidence its PCIe 6.0 interface...",
    "product": "PCIe 6.0 PHY and controller IP",
    "summary": "Cadence's PHY and controller IP for the PCIe 6.0 specification achieved first-pass compliance certification at a PCI-SIG compliance workshop.",
    "planning": false,
    "image_url": "https://www.myeverydaytech.com/wp-content/uploads/2026/09/Cadence-Subsystem-for-PCIe-6.0-Architecture-1.webp",
    "confidence": 0.9,
    "recognition": "PCI-SIG Integrators List",
    "product_data": {
      "name": "PCIe 6.0 PHY and controller IP",
      "full_text": "PHY and controller IP for the PCIe 6.0 specification",
      "fuzzy_match": false
    },
    "product_tags": [
      "general_technology"
    ],
    "published_at": "2026-09-22T12:56:38Z",
    "article_sentence": "Cadence has announced that its PHY and controller IP for the PCIe 6.0 specification, built on TSMC’s N3 process, achieved first-pass success at the recent PCI-SIG compliance workshop held in late July, the industry’s first official event for testing PCIe 6.0 compliance.",
    "related_company_name": "PCI-SIG",
    "related_company_domain": "pcisig.com"
  }
}

curl https://signals.autobound.ai/v1/signals/000c530e-6328-5ae9-9c5f-340dcd55e238 \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"cadence.com","limit":20}'