D-Matrix adopts NVLink Fusion for rack-scale AI inference
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The AI chip startup will plug its next-gen Raptor XPUs into NVIDIA's rack-scale fabric, targeting ultra-low-latency workloads by late 2027 Share Building your own AI chip is hard. Getting that chip into production racks at scale is arguably harder. D-Matrix, the inference-focused semiconductor startup, just announced a shortcut: it's wiring its next-generation Raptor XPUs directly into NVIDIA 's NVLink Fusion interconnect, gaining access to the entire rack-scale infrastructure that NVIDIA has spent years perfecting. The partnership means Raptor accelerators will connect through NVIDIA's sixth-generation NVLink fabric and slot into MGX reference architecture racks. Initial Raptor-based MGX systems are projected for 2027, with first units expected by Q4 of that year. NVLink Fusion, which NVIDIA introduced in 2025, lets third-party XPUs and CPUs tap into NVLink's low-latency links without building their own networking stack from scratch. The integration supports rack-scale configurations that can accommodate up to 144 Raptor accelerators within a single all-to-all NVLink domain. NVLink Fusion delivers 3x lower XPU-to-XPU latency compared to traditional Ethernet interconnects. Each XPU can access up to 3 TB/s of bandwidth through the sixth-generation NVLink fabric. D-Matrix CEO Sid Sheth has emphasized that the collaboration accelerates deployment for ultra-low-latency inference...
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