Lattice Semiconductor was granted a patent for faster programmable logic.

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  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-15T03:29:18+00:00",
  "company": {
    "name": "Lattice",
    "domain": "latticesemi.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H03K 19/1737"
      },
      {
        "code": "G06F 30/392",
        "label": "Electric digital data processing"
      },
      {
        "code": "H03K 19/17728"
      }
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    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Product Development"
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    "detail": "In September 2026 Lattice Semiconductor patented multi-mode logic blocks for programmable devices used in communications, industrial equipment, and embedded electronics.",
    "summary": "Lattice Semiconductor was granted a patent for faster programmable logic.",
    "event_at": "2026-09-08",
    "inventors": [
      {
        "name": "Bradley A. Sharpe-Geisler",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/brad-sharpe-geisler-069589121"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-08",
    "source_url": "https://patents.google.com/patent/US12732191",
    "cpc_primary": {
      "code": "H03K 19/1737"
    },
    "patent_title": "High-speed multi-mode logic block with combined outputs for programmable logic devices",
    "patent_number": "US12732191",
    "uspto_assignee": "Lattice Semiconductor Corporation",
    "patent_abstract": "Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.",
    "precision_class": "structural",
    "invention_explanation": "A programmable logic block that combines outputs from multiple lookup tables and ripple logic so one hardware section can perform more operations at high speed.",
    "technologies_mentioned": [
      "programmable logic devices",
      "FPGA logic blocks",
      "lookup tables",
      "digital logic"
    ]
  }
}

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