Qualcomm was granted a patent for variable-thickness chip interconnects.

{
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  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-10-21T16:33:38+00:00",
  "company": {
    "name": "Qualcomm",
    "domain": "qualcomm.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10W 70/65"
      },
      {
        "code": "H10W 70/611"
      },
      {
        "code": "H10W 70/685"
      },
      {
        "code": "H10W 90/00"
      },
      {
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    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Consumer Technology"
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    "detail": "In October 2026 Qualcomm patented semiconductor packaging for connecting integrated devices in compact electronic hardware while accommodating different interconnect thicknesses.",
    "summary": "Qualcomm was granted a patent for variable-thickness chip interconnects.",
    "event_at": "2026-10-20",
    "inventors": [
      {
        "name": "Aniket Patil",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/aniketpatilasu"
      },
      {
        "name": "Brigham Navaja",
        "status": "unresolved",
        "is_primary": false
      },
      {
        "name": "Hong Bok We",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/martin-hong-bok-we-6802645"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-10-20",
    "source_url": "https://patents.google.com/patent/US12772884",
    "cpc_primary": {
      "code": "H10W 70/65"
    },
    "patent_title": "Package comprising an integrated device and a metallization portion with variable thickness metallization interconnects on a same metal layer",
    "patent_number": "US12772884",
    "uspto_assignee": "QUALCOMM INCORPORATED",
    "patent_abstract": "A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness. The package may include a substrate and/or a bridge. The substrate may include an interposer.",
    "precision_class": "structural",
    "invention_explanation": "A chip package that places metal connections of different thicknesses on the same layer to support varied electrical and packaging needs.",
    "technologies_mentioned": [
      "semiconductor packaging",
      "chip interconnects",
      "metallization"
    ]
  }
}

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curl -X POST https://signals.autobound.ai/v1/companies/enrich \
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