SK hynix was granted a patent for a semiconductor plug structure.

{
  "signal_id": "05f7e6f2-a324-5392-8ece-c1dc9009f06e",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-10-30T01:11:51+00:00",
  "company": {
    "name": "SK Hynix",
    "domain": "skhynix.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10W 20/435"
      },
      {
        "code": "H10D 62/10",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      },
      {
        "code": "H10D 62/405",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      },
      {
        "code": "H10W 20/4403"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Product Development"
    ],
    "detail": "In October 2026 SK hynix patented vertically aligned plug connections for semiconductor devices, supporting compact and reliable chip fabrication.",
    "summary": "SK hynix was granted a patent for a semiconductor plug structure.",
    "event_at": "2026-10-27",
    "inventors": [
      {
        "name": "Young Gwang Yoon",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/young-gwang-yoon-8201a2287"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-10-27",
    "source_url": "https://patents.google.com/patent/US12777918",
    "cpc_primary": {
      "code": "H10W 20/435"
    },
    "patent_title": "Semiconductor device including a plug structure",
    "patent_number": "US12777918",
    "uspto_assignee": "SK hynix Inc.",
    "patent_abstract": "A semiconductor device includes a substrate having a first active region and a second active region; a first ion implantation region in the first active region of the substrate; a first plug structure over the first active region to be vertically aligned with the first ion implantation region; a second ion implantation region in the second active region of the substrate; and a second plug structure over the second active region to be vertically aligned with the second ion implantation region. The first ion implantation region includes a first outer ion implantation region and a first inner ion implantation region. The first outer ion implantation region surrounds at least one surface of the first inner ion implantation region. The first outer ion implantation region includes at least one of carbon (C) ions and fluorine (F) ions. The first inner ion implantation region includes at least one of germanium (Ge) ions and boron (B) ions.",
    "precision_class": "structural",
    "invention_explanation": "A chip design that lines up conductive plugs with implanted regions in separate parts of the substrate to connect device structures efficiently.",
    "technologies_mentioned": [
      "semiconductor devices",
      "plug structures",
      "ion implantation"
    ]
  }
}

curl https://signals.autobound.ai/v1/signals/05f7e6f2-a324-5392-8ece-c1dc9009f06e \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"skhynix.com","limit":20}'