An Epyc trip to Venice: Everything we do and don't know about AMD's 256-core monster chip

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    "url": "https://www.theregister.com/systems/2026/09/23/an-epyc-trip-to-venice-everything-we-do-and-dont-know-about-amds-256-core-monster-chip/5298614",
    "title": "An Epyc trip to Venice: Everything we do and don't know about AMD's 256-core monster chip",
    "excerpt": "systems 16 channels of DDR5, 5 GHz clock speeds, and support for CXL 3.1 memory god boxes? What's not to like? AMD's Venice Epycs mark the chipmaker's biggest architectural shift in CPU design since Rome made its debut all the way back in 2019. What's more, AMD's Zen 6-based product stack is shaping up to be the broadest CPU portfolio ever, spanning general purpose, HPC, AI, and eventually consumer platforms. AMD isn't quite ready to spill all the beans on its 6th-gen Zen cores, but at this point there's less we don't know about Venice than we do. Late last week, AMD gave us a bit more to chew on with a whitepaper [PDF] clearly aimed at quashing marketing juggernaut Nvidia's narrative around its Vera CPUs. We'll dive into the performance claims raised in the white paper in a bit, but given the piecemeal release of info on Venice up to this point, we figured it was time to take a closer look at the CPU architecture that will underpin AMD's roadmap for the next few years. Broadly speaking, AMD's 6th-gen lineup can be broken down into four buckets - high-performance, enterprise, HPC, and AI - each with its own quirks. We'll kick things off with AMD's performance-optimized parts because those are the ones that will actually ship in 2026. Pretty much everything else will be rolling out over the course of 2027. The Epyc 9006 SP7 platform is what AMD has really been talking about for...",
    "product": "Venice-X CPU",
    "summary": "AMD is developing its HPC-centric Venice-X CPUs, which will feature up to 1,152 MB of L3 cache per socket using its 3D V-Cache packaging technology.",
    "planning": true,
    "image_url": "https://image.theregister.com/5298634.jpg?imageId=5298634&x=0&y=0&cropw=100&croph=100&panox=0&panoy=0&panow=100&panoh=100&width=1200&height=683",
    "confidence": 0.9,
    "product_data": {
      "name": "Venice-X CPU",
      "full_text": "HPC centric Venice-X parts",
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    "published_at": "2026-09-23T15:51:11Z",
    "article_sentence": "Before we move on to AMD's more mainstream Epyc offerings, we should talk a bit more about its HPC centric Venice-X parts, which share the SP7 socket, but push L3 cache per core to 12 MB or 1,152 MB per socket."
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