Astera Labs was granted a patent for seamless low-latency clock switching.

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  "detected_at": "2026-10-14T15:45:11+00:00",
  "company": {
    "name": "Astera Labs",
    "domain": "asteralabs.com"
  },
  "data": {
    "cpc": [
      {
        "code": "G06F 1/12",
        "label": "Electric digital data processing"
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    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Data Center",
      "Network"
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    "detail": "In October 2026 Astera Labs patented retimer technology for data-center interconnects, maintaining reliable high-speed signaling when systems switch between clock sources.",
    "summary": "Astera Labs was granted a patent for seamless low-latency clock switching.",
    "event_at": "2026-10-13",
    "inventors": [
      {
        "name": "Jitendra Mohan",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/jitendramohan"
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      {
        "name": "Vikas Khandelwal",
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        "linkedin_url": "https://www.linkedin.com/in/vikas-khandelwal-15a1301"
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    ],
    "tech_area": "software / computing",
    "event_kind": "grant_date",
    "grant_date": "2026-10-13",
    "source_url": "https://patents.google.com/patent/US12761688",
    "cpc_primary": {
      "code": "G06F 1/12",
      "label": "Electric digital data processing"
    },
    "patent_title": "Low-latency retimer with seamless clock switchover",
    "patent_number": "US12761688",
    "uspto_assignee": "Astera Labs, Inc.",
    "patent_abstract": "A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.",
    "precision_class": "structural",
    "invention_explanation": "A signal-timing circuit that changes between slightly unsynchronized clocks without stretching or shortening clock pulses, preventing interruptions in data transmission.",
    "technologies_mentioned": [
      "signal retiming",
      "clock synchronization",
      "high-speed interconnects"
    ]
  }
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  -d '{"domain":"asteralabs.com","limit":20}'