US patent US12751341
Semiconductor assemblies with system and methods for aligning dies using registration marks
Abstract
Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.