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MicronPatent grant

Micron was granted a patent for aligning dies in semiconductor assemblies

What happened

In September 2026 Micron patented registration-mark structures for accurately stacking and aligning semiconductor dies in advanced chip packages.

Source

Abstract

Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.

patents.google.com/patent/US12751341Read the full source

Extracted by Autobound

From the Signal API record
Signal
Patent grant

What this signalsA new patent often shows where a company is putting its R&D budget.

Grant date
Sep 29, 2026
Inventors
Shiro Uchiyama
Patent number
US12751341
Assignee
Micron Technology, Inc.

The full record

From the Signal API record

People

  • Shiro UchiyamaInventor

Details

Primary CPC class
H10W 90/00
USPTO assignee
Micron Technology, Inc.
What the invention does
A package design that uses matching marks and channels to line up multiple chip dies during assembly.

Topics and mentions

Tags

  • Intellectual Property
  • Research & Development
  • Engineering
  • Manufacturing Operations

Technologies named

  • semiconductor packaging
  • die alignment
  • registration marks
  • chip assembly

Extraction

Detected
Sep 30, 2026
signal_type
patents-company
signal_subtype
patentGrant

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This page shows a preview. The full patents-company record in the Signal API and MCP can also have these 8 fields. Some fields are empty for some signals.

Company

  • linkedin_urlValue in the API
  • industriesValue in the API
  • employee_count_lowValue in the API
  • employee_count_highValue in the API
  • revenueValue in the API
  • descriptionValue in the API

Signal

  • signal_nameValue in the API
  • associationValue in the API
Show the full JSONThe record on this page and the API request

GET /v1/signals/17e47cb8-dbdc-5b67-ad09-ff45158f5bfc returns this record as JSON. POST /v1/companies/enrich returns every signal for micron.com.

{
  "signal_id": "17e47cb8-dbdc-5b67-ad09-ff45158f5bfc",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-30T17:49:14+00:00",
  "company": {
    "name": "Micron",
    "domain": "micron.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10W 90/00"
      },
      {
        "code": "H10W 46/00"
      },
      {
        "code": "H10W 95/00"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Manufacturing Operations"
    ],
    "detail": "In September 2026 Micron patented registration-mark structures for accurately stacking and aligning semiconductor dies in advanced chip packages.",
    "summary": "Micron was granted a patent for aligning dies in semiconductor assemblies",
    "event_at": "2026-09-29",
    "inventors": [
      {
        "name": "Shiro Uchiyama",
        "status": "unresolved",
        "is_primary": true
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-29",
    "source_url": "https://patents.google.com/patent/US12751341",
    "cpc_primary": {
      "code": "H10W 90/00"
    },
    "patent_title": "Semiconductor assemblies with system and methods for aligning dies using registration marks",
    "patent_number": "US12751341",
    "uspto_assignee": "Micron Technology, Inc.",
    "patent_abstract": "Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.",
    "precision_class": "structural",
    "invention_explanation": "A package design that uses matching marks and channels to line up multiple chip dies during assembly.",
    "technologies_mentioned": [
      "semiconductor packaging",
      "die alignment",
      "registration marks",
      "chip assembly"
    ]
  }
}

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