SK hynix was granted a patent for a new 3D memory structure.

{
  "signal_id": "06a1ceb4-bf2f-567e-97f8-e76198417ed9",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-10-30T01:06:16+00:00",
  "company": {
    "name": "SK Hynix",
    "domain": "skhynix.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10B 12/30"
      },
      {
        "code": "H10B 12/03"
      },
      {
        "code": "H10B 12/05"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Product Development"
    ],
    "detail": "In October 2026 SK hynix patented stacked semiconductor architecture for higher-density memory chips used in computing and electronic devices.",
    "summary": "SK hynix was granted a patent for a new 3D memory structure.",
    "event_at": "2026-10-27",
    "inventors": [
      {
        "name": "Gil Seop Kim",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/gil-seop-kim-3521ab243"
      },
      {
        "name": "Seung Hwan Kim",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/seung-hwan-kim-72464680"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-10-27",
    "source_url": "https://patents.google.com/patent/US12777631",
    "cpc_primary": {
      "code": "H10B 12/30"
    },
    "patent_title": "Semiconductor device and method for fabricating the same",
    "patent_number": "US12777631",
    "uspto_assignee": "SK hynix Inc.",
    "patent_abstract": "A semiconductor device includes: a lower structure; a first cell isolation layer and a second cell isolation layer stacked in a direction perpendicular to the lower structure and each including a void; a horizontal layer disposed between the first cell isolation layer and the second cell isolation layer; a first horizontal conductive line disposed between the first cell isolation layer and the horizontal layer, and a second horizontal conductive line disposed between the second cell isolation layer and the horizontal layer; a vertical conductive line coupled to a first side of the horizontal layer; and a data storage element including a first electrode coupled to a second side of the horizontal layer, and disposed between the first cell isolation layer and the second cell isolation layer.",
    "precision_class": "structural",
    "invention_explanation": "A layered memory design that places conductive lines and insulating barriers around engineered gaps to pack storage cells more efficiently.",
    "technologies_mentioned": [
      "3D memory",
      "semiconductor fabrication",
      "memory cells"
    ]
  }
}

curl https://signals.autobound.ai/v1/signals/06a1ceb4-bf2f-567e-97f8-e76198417ed9 \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"skhynix.com","limit":20}'