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SK HynixPatent grant

SK hynix was granted a patent for semiconductor failure-location detection.

What happened

In September 2026 SK hynix patented memory-test technology for identifying defective cells and their addresses during semiconductor manufacturing and quality checks.

Source

patents.google.comSep 29, 2026

US patent US12749551

Semiconductor system for detecting fail location

Abstract

A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.

patents.google.com/patent/US12749551Read the full source

Extracted by Autobound

From the Signal API record
Signal
Patent grant

What this signalsA new patent often shows where a company is putting its R&D budget.

Grant date
Sep 29, 2026
Inventors
Dong Yoon Ka
Patent number
US12749551
Assignee
SK hynix Inc.

The full record

From the Signal API record

People

  • Dong Yoon KaInventor

Details

Primary CPC class
G11C 29/36
USPTO assignee
SK hynix Inc.
What the invention does
A memory chip outputs test results with error addresses, while a processing circuit converts them into a map showing where failures occurred.

Topics and mentions

Tags

  • Intellectual Property
  • Research & Development
  • Manufacturing Operations
  • Quality Assurance

Technologies named

  • semiconductor testing
  • memory circuits
  • failure analysis

Extraction

Detected
Sep 30, 2026
signal_type
patents-company
signal_subtype
patentGrant

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  • signal_nameValue in the API
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GET /v1/signals/0a387960-41bf-5baf-97f5-636de798a659 returns this record as JSON. POST /v1/companies/enrich returns every signal for skhynix.com.

{
  "signal_id": "0a387960-41bf-5baf-97f5-636de798a659",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-30T17:28:16+00:00",
  "company": {
    "name": "SK Hynix",
    "domain": "skhynix.com"
  },
  "data": {
    "cpc": [
      {
        "code": "G11C 29/36"
      },
      {
        "code": "G11C 29/1201"
      },
      {
        "code": "G11C 29/18"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Manufacturing Operations",
      "Quality Assurance"
    ],
    "detail": "In September 2026 SK hynix patented memory-test technology for identifying defective cells and their addresses during semiconductor manufacturing and quality checks.",
    "summary": "SK hynix was granted a patent for semiconductor failure-location detection.",
    "event_at": "2026-09-29",
    "inventors": [
      {
        "name": "Dong Yoon Ka",
        "status": "unresolved",
        "is_primary": true
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-29",
    "source_url": "https://patents.google.com/patent/US12749551",
    "cpc_primary": {
      "code": "G11C 29/36"
    },
    "patent_title": "Semiconductor system for detecting fail location",
    "patent_number": "US12749551",
    "uspto_assignee": "SK hynix Inc.",
    "patent_abstract": "A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.",
    "precision_class": "structural",
    "invention_explanation": "A memory chip outputs test results with error addresses, while a processing circuit converts them into a map showing where failures occurred.",
    "technologies_mentioned": [
      "semiconductor testing",
      "memory circuits",
      "failure analysis"
    ]
  }
}

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