Cadence was granted a patent for balancing buffers in clock-tree layouts.

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  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-23T15:07:03+00:00",
  "company": {
    "name": "Cadence",
    "domain": "cadence.com"
  },
  "data": {
    "cpc": [
      {
        "code": "G06F 30/396",
        "label": "Electric digital data processing"
      },
      {
        "code": "G06F 30/347",
        "label": "Electric digital data processing"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Software"
    ],
    "detail": "In September 2026 Cadence patented chip-design software for improving clock distribution across integrated circuits by placing buffers along H-tree wiring.",
    "summary": "Cadence was granted a patent for balancing buffers in clock-tree layouts.",
    "event_at": "2026-09-22",
    "inventors": [
      {
        "name": "Yi-Xiao Ding",
        "status": "unresolved",
        "is_primary": true
      },
      {
        "name": "Zhuo Li",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/zhuoli"
      },
      {
        "name": "Charles Jay Alpert",
        "status": "unresolved",
        "is_primary": false
      }
    ],
    "tech_area": "software / computing",
    "event_kind": "grant_date",
    "grant_date": "2026-09-22",
    "source_url": "https://patents.google.com/patent/US12743573",
    "cpc_primary": {
      "code": "G06F 30/396",
      "label": "Electric digital data processing"
    },
    "patent_title": "Balancing buffer insertion for clock H-trees",
    "patent_number": "US12743573",
    "uspto_assignee": "Cadence Design Systems, Inc.",
    "patent_abstract": "Aspects of the present disclosure include system, methods, and software for creating an H-tree routing layout. In one example, a method includes an H-tree routing layout that has a plurality of vertical traces and horizontal traces connecting a clock source to a plurality of clock sinks. The method positions a plurality of candidate buffers in the H-tree routing layout. The method assigns a 4-dimensional (4D) vector to each candidate buffer of the plurality of candidate buffers, and derives one or more merge buffer combinations from the plurality of candidate buffers based on the assigned 4D vector of at least two candidate buffers of the plurality of candidate buffers. The method also applies a threshold vector to select one or more final candidate buffers from the merge buffer combinations.",
    "precision_class": "structural",
    "invention_explanation": "A method that scores possible buffer locations in a branching clock network and uses those scores to distribute timing support more evenly.",
    "technologies_mentioned": [
      "electronic design automation",
      "clock-tree synthesis",
      "integrated-circuit design",
      "buffer placement"
    ]
  }
}

curl https://signals.autobound.ai/v1/signals/65fe4cb7-5f88-5eee-bcdf-b205c4e6ad36 \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"cadence.com","limit":20}'