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SK HynixPatent grant

SK hynix was granted a patent for an improved memory-device architecture

What happened

In September 2026 SK hynix patented a transistor arrangement for controlling nonvolatile memory cells in solid-state storage and other electronic devices.

Source

patents.google.comSep 29, 2026

US patent US12749534

Memory device and method of operating the memory device

Abstract

Provided herein is a memory device and a method of operating the memory device. The memory device includes a string connected between a bit line and a source line, wherein the string includes one or more memory cells, a drain select transistor connected between the one or more memory cells and the bit line, and first and second source select transistors and a buffer source select transistor connected between the one or more memory cells and the source line, wherein the first and second source select transistors have different threshold voltages, and the buffer source select transistor is in an erase state.

patents.google.com/patent/US12749534Read the full source

Extracted by Autobound

From the Signal API record
Signal
Patent grant

What this signalsA new patent often shows where a company is putting its R&D budget.

Grant date
Sep 29, 2026
Inventors
Moon Sik Seo
Patent number
US12749534
Assignee
SK hynix Inc.

The full record

From the Signal API record

People

  • Moon Sik SeoInventor

Details

Primary CPC class
G11C 16/10
USPTO assignee
SK hynix Inc.
What the invention does
A memory circuit that uses multiple source-side switching transistors to control current through a row of memory cells during reading and writing.

Topics and mentions

Tags

  • Intellectual Property
  • Research & Development
  • Consumer Technology
  • Engineering

Technologies named

  • nonvolatile memory
  • memory cells
  • transistors
  • solid-state storage

Extraction

Detected
Sep 30, 2026
signal_type
patents-company
signal_subtype
patentGrant

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  • industriesValue in the API
  • employee_count_lowValue in the API
  • employee_count_highValue in the API
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  • descriptionValue in the API

Signal

  • signal_nameValue in the API
  • associationValue in the API
Show the full JSONThe record on this page and the API request

GET /v1/signals/2736d4bf-1b27-528f-9ea4-cfc1d56a74d5 returns this record as JSON. POST /v1/companies/enrich returns every signal for skhynix.com.

{
  "signal_id": "2736d4bf-1b27-528f-9ea4-cfc1d56a74d5",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-30T17:28:02+00:00",
  "company": {
    "name": "SK Hynix",
    "domain": "skhynix.com"
  },
  "data": {
    "cpc": [
      {
        "code": "G11C 16/10"
      },
      {
        "code": "G11C 16/0483"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Consumer Technology",
      "Engineering"
    ],
    "detail": "In September 2026 SK hynix patented a transistor arrangement for controlling nonvolatile memory cells in solid-state storage and other electronic devices.",
    "summary": "SK hynix was granted a patent for an improved memory-device architecture",
    "event_at": "2026-09-29",
    "inventors": [
      {
        "name": "Moon Sik Seo",
        "status": "unresolved",
        "is_primary": true
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-29",
    "source_url": "https://patents.google.com/patent/US12749534",
    "cpc_primary": {
      "code": "G11C 16/10"
    },
    "patent_title": "Memory device and method of operating the memory device",
    "patent_number": "US12749534",
    "uspto_assignee": "SK hynix Inc.",
    "patent_abstract": "Provided herein is a memory device and a method of operating the memory device. The memory device includes a string connected between a bit line and a source line, wherein the string includes one or more memory cells, a drain select transistor connected between the one or more memory cells and the bit line, and first and second source select transistors and a buffer source select transistor connected between the one or more memory cells and the source line, wherein the first and second source select transistors have different threshold voltages, and the buffer source select transistor is in an erase state.",
    "precision_class": "structural",
    "invention_explanation": "A memory circuit that uses multiple source-side switching transistors to control current through a row of memory cells during reading and writing.",
    "technologies_mentioned": [
      "nonvolatile memory",
      "memory cells",
      "transistors",
      "solid-state storage"
    ]
  }
}

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