US patent US12749534
Memory device and method of operating the memory device
Abstract
Provided herein is a memory device and a method of operating the memory device. The memory device includes a string connected between a bit line and a source line, wherein the string includes one or more memory cells, a drain select transistor connected between the one or more memory cells and the bit line, and first and second source select transistors and a buffer source select transistor connected between the one or more memory cells and the source line, wherein the first and second source select transistors have different threshold voltages, and the buffer source select transistor is in an erase state.