TSMC Concedes Intel’s EMIB Packaging Is A Potent Contender, Starts Building “Quasi-EMIB” As CoWoS Remains Choked Through 2026
Article excerpt
With TSMC's CoWoS advanced capacity egregiously constrained, and Intel's more nimble EMIB attracting a growing volume of orders, the Taiwan-based chipmaker has realized that it needs to change course to retain its competitive edge. And, it has chosen to do so by attempting to clone some elements of Intel's novel approach to advanced packaging, as per the reporting by The Information. For the benefit of those who might not be aware, TSMC's Chip-on-Wafer-on-Substrate (CoWoS-S) packaging solution uses large, expensive silicon interposers to connect processors with High Bandwidth Memory (HBM). This is essentially a full-surface silicon interposer layer, replete with a uniform grid of micro-bumps across the entire bottom surface of the die, where they serve as an interconnect medium. TSMC revamped this approach with CoWoS-L, which scraps the massive, continuous sheet of silicon interposer entirely, replacing it with a flexible, lower-cost Redistribution Layer (RDL) substrate. What's more, underneath this substrate, tiny localized silicon bridges - called Local Silicon Interconnects (LSI) - are embedded only at the precise boundaries where chiplets need to exchange dense data. This approach combines the high-speed data transmission of silicon with the massive, cost-effective surface area of organic RDL substrates. Even so, Intel's Embedded Multi-die Interconnect Bridge (EMIB) is...
Keep reading with a free account
The rest of this article, and every signal for TSMC, is in your free account.
Extracted from this sentence
According to The Information, TSMC is now developing an "EMIB-like" packaging solution with Kinsus Interconnect Technology Corp.
