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TSMC Concedes Intel’s EMIB Packaging Is A Potent Contender, Starts Building “Quasi-EMIB” As CoWoS Remains Choked Through 2026

What happened

TSMC is partnering with Kinsus Interconnect Technology Corp. to develop a new packaging solution similar to Intel's EMIB.

Source

Article excerpt

With TSMC's CoWoS advanced capacity egregiously constrained, and Intel's more nimble EMIB attracting a growing volume of orders, the Taiwan-based chipmaker has realized that it needs to change course to retain its competitive edge. And, it has chosen to do so by attempting to clone some elements of Intel's novel approach to advanced packaging, as per the reporting by The Information. For the benefit of those who might not be aware, TSMC's Chip-on-Wafer-on-Substrate (CoWoS-S) packaging solution uses large, expensive silicon interposers to connect processors with High Bandwidth Memory (HBM). This is essentially a full-surface silicon interposer layer, replete with a uniform grid of micro-bumps across the entire bottom surface of the die, where they serve as an interconnect medium. TSMC revamped this approach with CoWoS-L, which scraps the massive, continuous sheet of silicon interposer entirely, replacing it with a flexible, lower-cost Redistribution Layer (RDL) substrate. What's more, underneath this substrate, tiny localized silicon bridges - called Local Silicon Interconnects (LSI) - are embedded only at the precise boundaries where chiplets need to exchange dense data. This approach combines the high-speed data transmission of silicon with the massive, cost-effective surface area of organic RDL substrates. Even so, Intel's Embedded Multi-die Interconnect Bridge (EMIB) is...

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Extracted from this sentence

According to The Information, TSMC is now developing an "EMIB-like" packaging solution with Kinsus Interconnect Technology Corp.

Extracted by Autobound

From the Signal API record
Event
Partnership

What this signalsA new partnership often opens integration and co-selling work.

Companies

  • Kinsus Interconnect Technology Corp.Partnerkinsus.com.tw

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The full record

From the Signal API record

Extraction

Confidence
90%
Detected
Jul 30, 2026
signal_type
news
signal_subtype
partners_with

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This page shows a preview. The full news record in the Signal API and MCP can also have these 8 fields. Some fields are empty for some signals.

Company

  • linkedin_urlValue in the API
  • industriesValue in the API
  • employee_count_lowValue in the API
  • employee_count_highValue in the API
  • revenueValue in the API
  • descriptionValue in the API

Signal

  • signal_nameValue in the API
  • associationValue in the API
Show the full JSONThe record on this page and the API request

GET /v1/signals/9cc85d68-9fd2-b00b-3b57-7bc4c38f883d returns this record as JSON. POST /v1/companies/enrich returns every signal for tsmc.com.

{
  "signal_id": "9cc85d68-9fd2-b00b-3b57-7bc4c38f883d",
  "signal_type": "news",
  "signal_subtype": "partners_with",
  "detected_at": "2026-07-30T14:54:45+00:00",
  "company": {
    "name": "TSMC",
    "domain": "tsmc.com"
  },
  "data": {
    "url": "https://wccftech.com/tsmc-concedes-intels-emib-packaging-is-a-potent-contender-starts-building-quasi-emib-as-cowos-remains-choked-through-2026/",
    "title": "TSMC Concedes Intel’s EMIB Packaging Is A Potent Contender, Starts Building “Quasi-EMIB” As CoWoS Remains Choked Through 2026 - wccftech.com",
    "excerpt": "With TSMC's CoWoS advanced capacity egregiously constrained, and Intel's more nimble EMIB attracting a growing volume of orders, the Taiwan-based chipmaker has realized that it needs to change course to retain its competitive edge. And, it has chosen to do so by attempting to clone some elements of Intel's novel approach to advanced packaging, as per the reporting by The Information. For the benefit of those who might not be aware, TSMC's Chip-on-Wafer-on-Substrate (CoWoS-S) packaging solution uses large, expensive silicon interposers to connect processors with High Bandwidth Memory (HBM). This is essentially a full-surface silicon interposer layer, replete with a uniform grid of micro-bumps across the entire bottom surface of the die, where they serve as an interconnect medium. TSMC revamped this approach with CoWoS-L, which scraps the massive, continuous sheet of silicon interposer entirely, replacing it with a flexible, lower-cost Redistribution Layer (RDL) substrate. What's more, underneath this substrate, tiny localized silicon bridges - called Local Silicon Interconnects (LSI) - are embedded only at the precise boundaries where chiplets need to exchange dense data. This approach combines the high-speed data transmission of silicon with the massive, cost-effective surface area of organic RDL substrates . Even so, Intel's Embedded Multi-die Interconnect Bridge (EMIB) is...",
    "summary": "TSMC is partnering with Kinsus Interconnect Technology Corp. to develop a new packaging solution similar to Intel's EMIB.",
    "planning": true,
    "image_url": "https://cdn.wccftech.com/wp-content/uploads/2024/01/TSMC-Intel-Apple-Main-1920x1113.jpg",
    "confidence": 0.9,
    "published_at": "2026-07-30T14:54:45Z",
    "article_sentence": "According to The Information, TSMC is now developing an \"EMIB-like\" packaging solution with Kinsus Interconnect Technology Corp.",
    "related_company_name": "Kinsus Interconnect Technology Corp.",
    "related_company_domain": "kinsus.com.tw"
  }
}

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