Post: "Is this highest speed Adc on a microcontroller?"
r/embedded
Extracted from these lines
[comment u/somewhereAtC] Check with tech support at Microchip.com. They should have people with dsPIC experience that help adjust the clock issues.
“Use a RP2040/2050 with the PIO-Engine and dump the data using HDMI raw buffers. The PIO is needed to controll the annoying GPIO-Toggling of high-speed ADCs. The HDMI gives you ~175MB/s to the host which then can gather the data using a framegrabber. Costs around $10-20 and a bit of big-wire soldering.”
u/JuggernautGuilty56642 points · Aug 31, 2026View
“Only 64k of acquisition memory, so 32k samples? Very very niche at that point, and certainly most people doing things with FPGAs would expect that a mere 100Ms/s would interface directly at full speed, that isn't even something that really needs LVDS even on the slowest speed grade parts. As a student toy it might have some value, let them build a temu digital scope or such, but 64k? Without i”
u/dmills_0017 points · Aug 31, 2026View
“I love see this type contents on here,thanks for good post”
u/lecodeco123 points · Aug 31, 2026View
“What is your clock? You will need extremely low jitter. And the interleave on the microcontroller may add jitter that may not be possible to easily remove”
u/einthecorgi22 points · Aug 31, 2026View
“FYI, there are other MCUs that have faster ADCs (on paper, anyway). Take a look at NXP 4370. 12bit 80Msps ADC, triple core, USB, ethernet, etc.”
u/y00fie2 points · Aug 31, 2026View
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"summary": "A commenter on a post about a custom ADC board recommends contacting Microchip's tech support for their expertise with dsPIC microcontrollers to resolve clock issues.",
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"url": "https://www.reddit.com/r/embedded/comments/1w37lvh/comment/p6y10qn/",
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"author": "JuggernautGuilty566",
"excerpt": "Use a RP2040/2050 with the PIO-Engine and dump the data using HDMI raw buffers.\n\n The PIO is needed to controll the annoying GPIO-Toggling of high-speed ADCs. The HDMI gives you ~175MB/s to the host which then can gather the data using a framegrabber.\n\n Costs around $10-20 and a bit of big-wire soldering.",
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"excerpt": "Only 64k of acquisition memory, so 32k samples?\n\n Very very niche at that point, and certainly most people doing things with FPGAs would expect that a mere 100Ms/s would interface directly at full speed, that isn't even something that really needs LVDS even on the slowest speed grade parts.\n\n As a student toy it might have some value, let them build a temu digital scope or such, but 64k? Without i",
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"excerpt": "FYI, there are other MCUs that have faster ADCs (on paper, anyway). Take a look at NXP 4370. 12bit 80Msps ADC, triple core, USB, ethernet, etc.",
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"excerpt": "You could use two channels and make a direct quadrature sampling SDR receiver for the whole HF band!",
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