Samsung was granted a patent for a stacked semiconductor device.

{
  "signal_id": "071be95f-b8db-5d3b-8ab1-140f04a3ef93",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-30T17:48:37+00:00",
  "company": {
    "name": "Samsung",
    "domain": "samsung.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10W 20/435"
      },
      {
        "code": "H10B 43/10"
      },
      {
        "code": "H10B 43/27"
      },
      {
        "code": "H10B 43/35"
      },
      {
        "code": "H10B 43/40"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Consumer Technology"
    ],
    "detail": "In September 2026 Samsung patented layered semiconductor architecture for electronic systems, supporting compact, high-density memory and logic hardware.",
    "summary": "Samsung was granted a patent for a stacked semiconductor device.",
    "event_at": "2026-09-29",
    "inventors": [
      {
        "name": "Donghoon Kwon",
        "status": "unresolved",
        "is_primary": true
      },
      {
        "name": "Kihoon Jang",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/kihoon-jang-337916328"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-29",
    "source_url": "https://patents.google.com/patent/US12751279",
    "cpc_primary": {
      "code": "H10W 20/435"
    },
    "patent_title": "Semiconductor device and electronic system including semiconductor device",
    "patent_number": "US12751279",
    "uspto_assignee": "Samsung Electronics Co., Ltd.",
    "patent_abstract": "A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure connected to the circuit elements, and a peripheral region insulating layer covering the circuit elements; and a second semiconductor structure including a second substrate on the first substrate, a first stack structure including first and second gate electrodes spaced apart from each other and stacked on the second substrate, interlayer insulating layers alternately stacked with the first and second gate electrodes, first and second contact plugs passing through the first and second gate electrodes, and contact plug insulating layers alternately disposed with the interlayer insulating layers and surrounding the contact plugs. The second semiconductor structure includes a first capacitor structure including the first gate electrode, a contact plug insulating layer(s), and the second contact plug, or the second gate electrode, a contact plug insulating layer(s), and the first contact plug.",
    "precision_class": "structural",
    "invention_explanation": "A chip design that places circuit and transistor layers on top of one another, connecting them through insulating and wiring layers to fit more functionality into less space.",
    "technologies_mentioned": [
      "3D semiconductor integration",
      "stacked transistors",
      "electronic systems"
    ]
  }
}

curl https://signals.autobound.ai/v1/signals/071be95f-b8db-5d3b-8ab1-140f04a3ef93 \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"samsung.com","limit":20}'