A user describes the 'Identify' Integrated Logic Analyzer tool, part of the Synopsys Synplify synthesizer for Microchip FPGAs, as 'terrible' and having bugs that require workarounds.

{
  "signal_id": "050ae191-20d5-56b7-a75c-992d868e10df",
  "signal_type": "reddit-company",
  "signal_subtype": "customerFeedback",
  "detected_at": "2026-09-04T18:21:23+00:00",
  "company": {
    "name": "Synopsys",
    "domain": "synopsys.com"
  },
  "data": {
    "nsfw": false,
    "stage": "none",
    "awards": 0,
    "timing": "ongoing_state",
    "topics": [
      "eda",
      "fpga",
      "usability",
      "bugs",
      "developer tools"
    ],
    "post_id": "1w7cdv9",
    "summary": "A user describes the 'Identify' Integrated Logic Analyzer tool, part of the Synopsys Synplify synthesizer for Microchip FPGAs, as 'terrible' and having bugs that require workarounds.",
    "category": "usability",
    "comments": [
      {
        "url": "https://www.reddit.com/r/FPGA/comments/1w7cdv9/comment/p7vogwt/",
        "depth": 0,
        "score": 6,
        "author": "Quantum_Ripple",
        "excerpt": "Microchip FPGAs (including PolarFire SoC) actually do have an ILA equivalent provided by the Synplify synthesizer. It's called \"Identify\". You instrument signals by opening synthesis interactively. I will say, however, that it's terrible (typical for FPGA tools) and there are some bugs that you have to work around so your project is probably better.\n\n I might suggest looking into the UJTAG primiti",
        "posted_at": "2026-09-04T23:45:15.000Z",
        "author_url": "https://www.reddit.com/user/Quantum_Ripple/"
      }
    ],
    "evidence": [
      "[comment u/Quantum_Ripple] Microchip FPGAs (including PolarFire SoC) actually do have an ILA equivalent provided by the Synplify synthesizer. It's called \"Identify\".",
      "[comment u/Quantum_Ripple] I will say, however, that it's terrible (typical for FPGA tools) and there are some bugs that you have to work around so your project is probably better."
    ],
    "link_url": "https://www.reddit.com/gallery/1w7cdv9",
    "virality": "medium",
    "post_date": "2026-09-04T18:21:23.000Z",
    "post_kind": "gallery",
    "sentiment": "negative",
    "subreddit": "FPGA",
    "post_flair": [
      "Advice / Help"
    ],
    "post_title": "LibreILA: Open Source Integrated Logic Analyzer, would love feedback",
    "prominence": "aside",
    "source_url": "https://www.reddit.com/r/FPGA/comments/1w7cdv9/libreila_open_source_integrated_logic_analyzer/",
    "entity_role": "vendor",
    "post_author": "TrustMeIAmEEEEnginr",
    "upvote_ratio": 0.9736842105263158,
    "mention_count": 1,
    "mention_surge": false,
    "subreddit_url": "https://www.reddit.com/r/FPGA/",
    "total_upvotes": 36,
    "comments_total": 3,
    "total_comments": 3,
    "other_companies": [
      {
        "name": "Microchip Technology",
        "role": "partner",
        "domain": "microchip.com"
      }
    ],
    "post_author_url": "https://www.reddit.com/user/TrustMeIAmEEEEnginr/",
    "signal_category": "feedback",
    "comments_included": 1,
    "products_mentioned": [
      "Synplify",
      "Identify"
    ]
  }
}

curl https://signals.autobound.ai/v1/signals/050ae191-20d5-56b7-a75c-992d868e10df \
  -H "X-API-KEY: $AUTOBOUND_API_KEY"

curl -X POST https://signals.autobound.ai/v1/companies/enrich \
  -H "X-API-KEY: $AUTOBOUND_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{"domain":"synopsys.com","limit":20}'