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TSMCPatent grant

TSMC was granted a patent for a compact CFET power-grid design

What happened

In September 2026 TSMC patented a semiconductor layout that routes power through upper metal layers, supporting dense logic-chip manufacturing.

Source

Abstract

A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.

patents.google.com/patent/US12751268Read the full source

Extracted by Autobound

From the Signal API record
Signal
Patent grant

What this signalsA new patent often shows where a company is putting its R&D budget.

Grant date
Sep 29, 2026
Inventors
4
Patent number
US12751268
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

The full record

From the Signal API record

People

  • Kuan Yu ChenInventor
  • Chun-Yen LinInventor
  • Wei-Cheng TzengInventor
  • Wei-Cheng LinInventor
  • Shih-Wei PengInventor
  • Jiann-Tyng TzengInventor

Details

Primary CPC class
H10W 20/20
USPTO assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
What the invention does
A chip structure that places power rails in a higher wiring layer above vertically stacked transistors, helping deliver power without taking as much space near the devices.

Topics and mentions

Tags

  • Intellectual Property
  • Research & Development
  • Engineering
  • Manufacturing Operations

Technologies named

  • CFETs
  • semiconductor manufacturing
  • power-grid routing
  • metal interconnects

Extraction

Detected
Sep 30, 2026
signal_type
patents-company
signal_subtype
patentGrant

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This page shows a preview. The full patents-company record in the Signal API and MCP can also have these 8 fields. Some fields are empty for some signals.

Company

  • linkedin_urlValue in the API
  • industriesValue in the API
  • employee_count_lowValue in the API
  • employee_count_highValue in the API
  • revenueValue in the API
  • descriptionValue in the API

Signal

  • signal_nameValue in the API
  • associationValue in the API
Show the full JSONThe record on this page and the API request

GET /v1/signals/13fe3f64-68da-572f-a7ba-af94574abb73 returns this record as JSON. POST /v1/companies/enrich returns every signal for tsmc.com.

{
  "signal_id": "13fe3f64-68da-572f-a7ba-af94574abb73",
  "signal_type": "patents-company",
  "signal_subtype": "patentGrant",
  "detected_at": "2026-09-30T17:48:35+00:00",
  "company": {
    "name": "TSMC",
    "domain": "tsmc.com"
  },
  "data": {
    "cpc": [
      {
        "code": "H10W 20/20"
      },
      {
        "code": "H10D 84/017",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      },
      {
        "code": "H10D 84/0186",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      },
      {
        "code": "H10D 84/038",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      },
      {
        "code": "H10D 84/85",
        "label": "Inorganic electric semiconductor devices (2025 CPC reorg of parts of H01L)"
      }
    ],
    "tags": [
      "Intellectual Property",
      "Research & Development",
      "Engineering",
      "Manufacturing Operations"
    ],
    "detail": "In September 2026 TSMC patented a semiconductor layout that routes power through upper metal layers, supporting dense logic-chip manufacturing.",
    "summary": "TSMC was granted a patent for a compact CFET power-grid design",
    "event_at": "2026-09-29",
    "inventors": [
      {
        "name": "Kuan Yu Chen",
        "status": "resolved",
        "is_primary": true,
        "linkedin_url": "https://www.linkedin.com/in/kuan-yu-chen-15a90157"
      },
      {
        "name": "Chun-Yen Lin",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/yenchunlin24"
      },
      {
        "name": "Wei-Cheng Tzeng",
        "status": "unresolved",
        "is_primary": false
      },
      {
        "name": "Wei-Cheng Lin",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/wei-cheng-lin-b9a871a0"
      },
      {
        "name": "Shih-Wei Peng",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/shih-wei-peng-a1242011a"
      },
      {
        "name": "Jiann-Tyng Tzeng",
        "status": "resolved",
        "is_primary": false,
        "linkedin_url": "https://www.linkedin.com/in/jiann-tyng-tzeng-bb36b043"
      }
    ],
    "event_kind": "grant_date",
    "grant_date": "2026-09-29",
    "source_url": "https://patents.google.com/patent/US12751268",
    "cpc_primary": {
      "code": "H10W 20/20"
    },
    "patent_title": "Device having CFET with power grid rails in second metallization layer and method of manufacturing same",
    "patent_number": "US12751268",
    "uspto_assignee": "TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.",
    "patent_abstract": "A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.",
    "precision_class": "structural",
    "invention_explanation": "A chip structure that places power rails in a higher wiring layer above vertically stacked transistors, helping deliver power without taking as much space near the devices.",
    "technologies_mentioned": [
      "CFETs",
      "semiconductor manufacturing",
      "power-grid routing",
      "metal interconnects"
    ]
  }
}

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